1. Field of the Invention
This invention relates to isolation junctions for semiconductor devices.
2. BACKGROUND OF THE INVENTION
Integrated circuits and related semiconductor devices depend on electrical isolation of one component from another. The most common isolation technique for devices made in the same semiconductor wafer is a diffused region of conductivity type which is opposite to that of the bulk of the device. This results in back-to-back P-N junctions interposed between the devices. This process is usually accomplished by solid state diffusion of selected impurities in a pattern between the devices requiring isolation. The diffused isolation regions are tapered with the widest portion being at the surface through which the diffusion operation is performed. Consequently, the available surface area for component manufacture is reduced in size. Additionally, the diffused regions do not have a constant resistivity throughout the diffused region and the resulting P-N junctions formed thereby are not always a step junction. Occasionally, deep electrical isolation junctions require diffusion of impurities through opposed surfaces of the device. This requires extra process steps. In any instance, however, junction isolation of such devices requires high temperatures and extended furnace times such, for example, as 1250.degree. C for 3 days. High carrier lifetime and crystalline perfection of substrate material are degraded in spite of extensive efforts made to preserve them. Lateral diffusion during formation of the isolation junctions wastes a large volume of the substrate which could be used for device fabrication.
Other electrical isolation techniques involves selective etching of the substrate material of the device and growing or depositing silicon oxide in the etched portion of the substrate.
An object of this invention is to provide a new and improved junction isolation means in semiconductor devices which overcome the deficiencies of the prior art.
Another object of this invention is to provide a new and improved junction isolation means in a semiconductor device which optimizes the volume of substrate material available for device and circuit fabrication.
Another object of this invention is to provide a new and improved junction isolation means in a semiconductor device wherein the isolation region is substantially uniform in thickness and resistivity throughout the region.
A further object of this invention is to provide a new and improved junction isolation means in a semiconductor device wherein post diffusion of the P-N junction is practiced to alter the step junction to a graded junction.